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Krzysztof Bieganski

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Next big step for Verilator: towards four-state logic and UVM compatibilityLatch-Up 20262026-05-01
UVM 2017 and UVM 2020 compile with Verilator and nearly 100 pull requests land for scheduling (eager triggers, three‑stage scheduling, immediate finish)…
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Advancing design verification with VerilatorORConf 20252025-09-12
Project progress shows 21 of 33 UVM cookbook examples passing and the tool can now elaborate all of UVM 2017 without workarounds. Recent additions include…
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Open source design testing and verification with UVM and VerilatorORConf 20232023-09-15
Verilator now supports many non‑synthesizable SystemVerilog features enabling near‑complete UVM use: full class hierarchy and parameter resolution for UVM (all…
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