pyfda: Python Filter Design and Analysis
summary
Live demo of pyfda designs a decimation filter from 48 kHz → 24 kHz with a required Nyquist stop at 12 kHz and a target -60 dB stopband, then generates floating coefficients and shows fixed‑point quantization: default large format (about 19 bits) is reduced to 11-bit coefficients, which produces visible spec violations in the frequency response and longer settling in the transient. Shows poles/zeros, group delay, accumulator bit‑width choices for FPGA/microcontroller implementation and asks for help exporting/verifying HDL or domain‑specific code.
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chapters (5)
- 0:00Introduction to DSP tools
- 0:38Filter design and analysis
- 1:51Hardware implementation
- 2:57Testing with stimulus signals
- 4:20Hardware logic and collaboration
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