The Toy-SRAM Project
summary
An open-source multiport memory system replaces bespoke register-file circuits with a replicated 10T SRAM cell that separates reads and writes, enabling lower voltage operation (~0.4 V), higher speed and easy port scaling by replication. A working prototype targets 64 registers × 24 bits, uses three nonstandard cells in a mainly standard-cell wrapper, aims for double-data-rate/dual-clock operation to get two reads per half-cycle, and is planned for fab-friendly 130 nm 5LM silicon.
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chapters (5)
- 0:00Start
- 3:57Features of TOY-SRAM
- 8:43What is specific bandwidth? Why does Toy-SRAM do so well?
- 18:22Plans for TOY-SRAM
- 19:12Toy-SRAM key components
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