A fully open source memory controller targeting LPDDR4/5 for FPGA and ASIC us...
summary
A fully open source memory controller called LightDRAM targets LPDDR4/5 and other DDR standards, generates optimized Verilog from a Migen-based generator, and runs on hundreds to thousands of FPGA boards (including Digilent RT A7) while using far fewer resources than vendor controllers. It includes a pluggable PHY and LPDDR4/5 on older FPGAs support, a soft-CPU PHY training loop in C for eye calibration, AXI/Wishbone and DMA/L2 features, and ships under BSD 2-clause with no vendor code, and is being pushed toward SkyWater 130nm and GF 12LP ASIC flows.
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chapters (15)
- 0:00Introduction to LightDRAM
- 1:28What is DRAM and memory controller
- 5:48LightDRAM's scope and features
- 10:51PHY and high performance
- 13:44LightDRAM as a generator
- 15:56Open source and licensing
- 17:23PHY training and alignment
- 20:37Recent developments and LPDDR4
- 24:13Rowhammer attacks and research
- 28:25Future of Rowhammer mitigation
- 30:10Memory controller in data centers
- 31:59ASIC deployment plans
- 34:07Open source PDK and roadmap
- 36:35Chips Alliance collaboration
- 37:58Q&A session
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