The LibreSOC Initiative: A hybrid CPU/VPU/GPU
summary
LibreSOC builds a single-chip hybrid CPU/VPU/GPU by adding Simple‑V vector and 3D/video extensions to the Power ISA, implemented in a Python HDL (nMigen style) and tested on a Versa ECP5 FPGA; a basic core runs in simulation and FPGA now. Funding is €350,000 from NLNet, the next milestone is a low-cost 180nm test ASIC (~$18k per run) and an 18‑month target for a 28nm-class quad‑core SoC; two Vulkan/Mesa drivers plus FFmpeg video pieces are in development.
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chapters (13)
- 0:00OpenPOWER Summit
- 0:17Why another SoC?
- 2:55Why OpenPOWER? (but first: Evaluation Criteria)
- 6:16What goes into a typical Soc?
- 8:53Simple SBC-style SoC
- 10:07Where to start? (roadmap)
- 12:02What's different about Libre-SOC?
- 14:06Hybrid Architecture: Augmented 6600
- 16:32Why nmigen? (but first: evaluate other HDLS)
- 19:40amigen (dynamic) vs VHDL (static)
- 21:55nmigen Power SA Decoder
- 24:50Simple-V ADD in a nutshell
- 25:30Summary
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