AI Acceleration Capabilities Using MMA(Matrix Multiply...
summary
Power ISA v3.1 adds MMA: eight 512-bit accumulators mapped to VSRs that require explicit move-to/from operations, supporting fp64/fp32/fp16/bf16 and int16/int8/int4. One fp32 MMA issues 16 MACs (int8 64, int4 128) into a 512-bit accumulator; optimized kernels use an 8×16 submatrix pattern needing six loads and eight MMA ops per block. Toolchain support includes GCC-10 built-ins and OpenBLAS with Power10 core kernels; pre-silicon results show >4× per-core SGEMM vs Power9, ~10× fp32 ResNet-50, up to 20× lower-precision.
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chapters (11)
- 0:00Introduction
- 0:23Agenda
- 3:15Data Types Supported
- 5:03MMA Instruction Examples
- 6:27IBM Power 10
- 8:27Programming
- 11:20Single Precision
- 13:50Mixed and Lower Precision
- 15:10Community Adoption
- 16:42Performance
- 17:40QA
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