Keynote: Artificial Innovation Accelerates Artificial Intelligence
summary
Machine learning training needs far more compute but Moore’s Law slows, so architects build domain-specific hardware. Google ships TPUv1–v3: 256x256 MACs with 8-bit inference, TPUv2 adds a 500Gb/s per-link inner-core interconnect and two-core chips, TPUv3 runs up to 1024-chip TPUv3 clusters with liquid cooling and achieves ~980x speedup on AlphaZero and ~10x better performance-per-watt versus top Green500 systems. Berkeley’s RISC-V and the RIOS Lab push open, extensible ISAs and bfloat16 for efficient edge and training implementations.
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chapters (20)
- 0:00Introduction
- 0:15Artificial Intelligence
- 3:20Domain specific architectures
- 4:05Cloud vs Edge
- 4:38Deep Neural Networks
- 5:58Why was it successful
- 6:39TPU V2
- 8:11Inner Core Interconnect
- 9:09How Many Cores
- 10:15Supercomputer Arithmetic
- 12:20Supercomputer Floor Plan
- 12:41TPU V3
- 13:57Individual Chip Performance
- 15:43Scale Up
- 16:15Comparison
- 18:09Edge Computing
- 22:22Security
- 22:32Internet of Things
- 23:08Rios Lab
- 24:37Machine Learning
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