David Patterson
where else to find them
no profile links on file
what they talk about
all 6 in the filters
where they keep going back
- RISC-V Summit North America2 editions2024–2025
all 8 in the filters
on a stage with
- Amber Huffmanonce
- Andrea Galloonce
- John Hennessyonce
all 4 in the filters
who talks about the same things
- Chip Huyen10 talks
- Aaron Williams8 talks
- Kesha Williams7 talks
- Chris Lattner9 talks
- Tarry Singh7 talks
- Aparna Ramani7 talks
| title | conference | date |
|---|---|---|
| A RISCy Approach to Microprocessor Technology | RISC-V Summit North America 2025 | 2025-10-22 |
Berkeley designs a simple RISC ISA in 1980, teaches it through three courses, and sends student layouts to fabrication using in-house CAD, Unix tools and the… | ||
| Computer Architecture 101 and its Future | Algorithmic Foundations for Emerging Computing Technologies Boot Camp 2025 | 2025-09-08 |
Covers why Dennard scaling ends and Moore’s cadence slows, how servers now pack ~64–128 cores (two‑way SMT → ~256 threads) at 3–4.5 GHz with hundreds of… | ||
| Keynote: Instruction Sets Want to be Free - A 10 Year Retrospective | RISC-V Summit North America 2024 | 2024-10-22 |
Revisits the ten-year claim that an open ISA can evolve and scale, arguing evidence includes 400 organizations and 5,000 individual members, Berkeley’s eight… | ||
| Collaboration Breakfast | RISC-V Summit North America 2024 | 2024-10-22 |
Google hosts a software-focused breakfast about accelerating the RISC‑V ecosystem through Rise workgroups, upstream-first repos and cloud-access boards. Key… | ||
| Keynote: Artificial Innovation Accelerates Artificial Intelligence | Ray Summit 2020 | 2020-09-30 |
Machine learning training needs far more compute but Moore’s Law slows, so architects build domain-specific hardware. Google ships TPUv1–v3: 256x256 MACs with… | ||
| Keynote: The First Decade of RISC-V: A Worldwide Phenomenon | RISC-V Global Forum 2020 | 2020-09-03 |
Chronicles RISC‑V’s concrete milestones: creation on May 18, 2010, the RV32I reference implemented in days, adoption by companies (SiFive, Andes) and… | ||
| Code Size of RISC V versus ARM using the Embench™ 0 5 Benchmark Suite | RISC-V Summit 2019 | 2019-12-09 |
Comparison uses the Embench 0.5 benchmark suite and GCC to measure code size and speed across RISC‑V and ARM cores. Results show adding multiply/divide yields… | ||
| A New Golden Age for Computer Architecture | Berkeley ACM A.M. Turing Laureate Colloquium 2018 | 2018-09-26 |
History of instruction sets moves from microcode to RISC to open ISAs and domain-specific chips; claim is that raised software/hardware interfaces enable far… | ||
| Keynote Fireside Chat: Computer Architecture Past, Present, and Future | Google Cloud Next '18 | 2018-07-24 |
Survey of computing history leads to concrete claims: RISC now underpins 99% of machines, RISC replaces big CISC vocabularies with a small one and shows 25%… | ||
| MLPerf: A Benchmark Suite for Machine Learning – David Patterson | Artificial Intelligence Conference 2018 New York | 2018-04-30 |
About 20 contributors from five organizations (including three universities and three industry firms) form a cooperative called MLPerf that builds a benchmark… | ||
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