A New Golden Age for Computer Architecture
summary
History of instruction sets moves from microcode to RISC to open ISAs and domain-specific chips; claim is that raised software/hardware interfaces enable far bigger gains than transistor scaling. Evidence: Python matrix multiply is ~63,000× slower than fully optimized kernels; Spectre-style speculation leaks up to ~10,000 bits/sec; Itanium and iAPX432 fail in market; TPU v1 delivers ~90 TOPS with ~30× energy efficiency vs GPUs and ships in production; RISC-V plus FPGAs let teams iterate chips rapidly for domain-specific architectures.
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chapters (22)
- 0:00Start
- 5:57Control versus Datapath
- 6:53Microprogramming in IBM 360
- 8:28Writable Control Store
- 9:36Microprocessor Evolution
- 13:25Analyzing Microcoded Machines 1980s
- 16:44Berkeley and Stanford RISC Chips
- 17:55"Iron Law" of Processor Performance: How RISC can win
- 19:22CISC vs. RISC Today
- 23:07VLIW Issues and an "EPIC Failure"
- 27:03Technology & Power: Dennard Scaling
- 27:33End of Growth of Single Program Speed?
- 28:58Quantum Computing to the Rescue?
- 30:02Current Security Challenge
- 31:23What Opportunities Left? (Part 1)
- 37:08ML Training Trends
- 38:10TPU: High-level Chip Architecture
- 38:44Perf/Watt TPU vs CPU & GPU
- 43:44RISC-V Origin Story
- 45:11What's Different About RISC-V?
- 46:03Foundation Members since 2015
- 50:50Agile Hardware Development Methodology
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