The Real Challenge for RISC-V Vector Processors

on YouTube ↗17m

" summary

Argument: data movement, not compute, limits RVV performance, and Andes implements an ACE Streaming Port — a custom AXI-like data port plus dedicated memory and semi‑automatic co‑pilot tool to generate instructions and coprocessor logic — to feed accelerators with predictable latency and low power. Demonstrated gains include 20–60× acceleration on CPU workloads, MobileNet falling from 55 billion cycles to ~1.3 billion with vectors, FPGA runs at ~50–60 MHz show vector ≈1 minute vs DSP ≈4 minutes, baseline >20 minutes. Also supports bfloat16 and N4.

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" chapters (14)

1. 0:00Introduction and history
2. 0:21Processor wars and RISC
3. 1:47Frequency scaling challenges
4. 3:31Introduction to RISC-V
5. 5:02Traditional architecture issues
6. 5:43Vector engine architecture
7. 7:14Bandwidth and memory designs
8. 9:07Andes custom extensions
9. 10:34Streaming port implementation
10. 12:21AI specific data formatting
11. 13:21Semi-automated design
12. 14:30Processing element clusters
13. 15:15Performance benchmarks
14. 16:49Final thoughts and Q&A

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