Low-Cost SIMD Module for ML Acceleration
summary
Describes an open-source short SIMD module for accelerating ML on area- and power-constrained RISC-V cores by reusing the integer register file instead of adding a separate vector register file. The design adds 17 configurable custom instructions that combine SIMD ops with two-stage reductions (MAC-like) plus optional saturation, swizzling and masking, supports ~200 ML operation combinations, is portable across RISC-V cores and was integrated into the NOEL-V processor, yielding 3–7× speedups with a 25% area overhead.
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chapters (9)
- 0:00Start
- 0:20Introduction and Motivation
- 2:14Low-Cost Short Vector Support for Space Processprs
- 3:49SIMD: Architecture design
- 8:15SIMD: Programming
- 8:58Evaluation: Hardware Overhead
- 10:25Evaluation: ML Performance
- 11:54Conclusions and Future Work
- 13:19Additional information
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