Exploring Static Code Generation and SIMD-Acceleration for Machine Learning on RISC-V

on YouTube ↗17m

" summary

Presents two static code generators—one based on TensorFlow Lite for Microcontrollers and one based on TVM—that compile ML models into static executable code for RISC-V microcontrollers to eliminate runtime and memory overhead of dynamic model runtimes. Describes RISC-V CMSIS-NN kernel implementations that use the RISC-V P (packed/SIMD) and V (vector) extensions to accelerate inner loops, and reports evaluation results on TinyMLPerf using the ETISS simulator showing benefits of static code generation and SIMD-accelerated kernels.

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" chapters (8)

1. 0:00Introduction to ML on RISC-V
2. 3:04Static code generation process
3. 6:05SIMD and vector extensions
4. 8:00Open source toolchain support
5. 10:04Reference implementations and benchmarks
6. 11:17Performance comparison results
7. 13:12Runtime overhead analysis
8. 15:15Future frameworks and optimizations

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