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Panel: Toolchains & Runtime

Panelat RISC-V Forum: Developer Tools and Tool Chains 2021 · on Wednesday, 2021-06-02· at 18:35· Virtual· [developer-experience]
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name:K. Cheng
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name:J. Clarke
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name:J. Leidel
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slides:none on file

Panel reports that RISC-V’s scalable vector v1.0 work-in-progress brings many instructions but real compiler gaps remain: segmented loads/stores are awkward, vsetvl sideband bits block optimizations, and LLVM auto-vectorization is still naive while GCC is more stable. Practical fixes include intrinsics, builtin APIs, linker/ABI tweaks and indirect functions dispatch for multiple implementations. A public riscv-test.org CI runs weekly cross-compiler builds. Missing pieces for HPC: tuned BLAS/LAPACK/Trilinos, OpenUCX/InfiniBand drivers. Early bitmanip boosts string ops to ~6–7 cycles per word.

AI-written summary · about

  1. 0:00Intro
  2. 1:00Vector Extensions
  3. 1:50State of Vector Support
  4. 3:10Vector Length Specific Support
  5. 6:20LVM Support
  6. 6:55Use Cases
  7. 8:15Hand Optimization
  8. 8:50Vector Support
  9. 9:50Same Splitter
  10. 11:30Extensions
  11. 16:20Extension Policy
  12. 21:45String Functions
  13. 24:40Multiple Functions
  14. 28:50Libraries
  15. 31:20Roadmap
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