OVI: The Open Vector Interface
summary
OVI is an open protocol that wires a RISC‑V core to a loosely coupled vector unit and is already used to connect the Avispado core to the Vitruvius VPU and taped out test chip proves it works. The core keeps control CSRs and issues vector loads/stores while the VPU does arithmetic and private instructions; signals include a 32‑bit raw instruction bus, a credit system, sequence id for out‑of‑order memory and sync_start/sync_end to coordinate masked, indexed and fast‑stride (unit/2/4 and negatives) transfers. The spec imposes no VPU ordering model.
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chapters (7)
- 0:00Introduction
- 4:40Configuration and Memory
- 5:28Categories
- 6:17Signals
- 11:44Execution
- 17:52Store
- 18:31Summary
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