RISC-V Forum: Vector & Machine Learning 2021
2021-09-15
-- online --
| title | author | length |
|---|---|---|
| RISC-V Welcome | Thea Aldrich | 02m |
Three-hour online forum focuses on RISC-V vector and machine-learning work with SiFive listed as sponsor and RISC-V.org as the reference for the free and open… | ||
| Low-Cost SIMD Module for ML Acceleration | Marc Solé Bonet, Leonidas Kosmidis | 14m |
Low-Cost SIMD Module for ML Acceleration - Marc Solé Bonet & Leonidas Kosmidis, Universitat Politècnica de Catalunya (UPC) and Barcelona Supercomputing Center… | ||
| RISC-V Vector Sail Model and Test Generation | Yifei Zhu, Xi Wang | 20m |
A machine-readable Sail golden model for RISC‑V Vector (RVV) is implemented with configurable vector register widths, read/write helpers, CSR functions and… | ||
| An Efficient Implementation of TensorFlow Lite for RISC-V Vectors | Mostafa Hagog | 28m |
TensorFlow Lite runs natively on a RISC‑V vector core (x280) with full Linux, LLVM and GCC toolchains and a custom quantized int8 matrix multiplication… | ||
| Deep Dive: Accelerating Neural Networks using RVV and Open Standard Software | Mehdi Goli | 25m |
Ends-to-end workflow that compiles SYCL kernels to an RVV-enabled LLVM backend, injects low-level driver abstractions and a Codeplay vectorizer, and runs a… | ||
| Lightning Talk: Software Development for ML and RISC-V Vector Acceler... | Lee Moore, Simon Davidmann | 10m |
Imperas provides fast virtual platforms that boot Linux in ~15 seconds and simulate heterogeneous Arm + RISC-V arrays to develop software long before silicon… | ||
| OVI: The Open Vector Interface | Roger Espasa, Alberto Moreno | 20m |
OVI is an open protocol that wires a RISC‑V core to a loosely coupled vector unit and is already used to connect the Avispado core to the Vitruvius VPU and… | ||
| Lightning Talk: Using Embedded FPGAs for Custom Vector Extensions | Dirk Koch | 09m |
FABulous framework builds eFPGAs that plug reconfigurable custom instructions directly into a RISC-V core (example: FlexBex) and prototypes show these… | ||
| Lightning Talk: Design Verification with Step-and-Compare for RISC-V... | Lee Moore, Simon Davidmann | 09m |
Uses an asynchronous lockstep compare against an architectural “envelope” model that covers drafts and extensions, exporting GPRs FPRs CSRs and the vector… | ||
| The Real Challenge for RISC-V Vector Processors | John Min | 17m |
Argument: data movement, not compute, limits RVV performance, and Andes implements an ACE Streaming Port — a custom AXI-like data port plus dedicated memory… | ||
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