Porting SIMD to RISC-V Vectors | Corrected Audio
summary
Claims RISC-V Vector (RVV) matches modern SIMD: 32 vector registers, hardware VL between 128 bits and 64K, and support for predication, scatter/gather and register grouping (M1→M8). Hands-on C intrinsics target porting from Neon/AVX, using a provided toolchain + QEMU/musl to run tests. Exercises include literal-translation memcopy (16‑byte Neon → RVV), a dot‑product where placement of setvl/setvlmax matters, and an Adler‑32 port; watch for the tail undisturbed pitfall that produces NaNs if omitted.
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chapters (14)
- 0:00Introduction and setup
- 1:59SIMD overview and porting basics
- 10:05ARM Neon and SVE/SVE2 comparison
- 23:27First hands-on session setup
- 38:24Memcopy exercise walkthrough
- 40:11Loop patterns and design principles
- 50:21Register grouping in RISC-V Vectors
- 1:00:19Second hands-on session setup
- 1:08:37Q&A and exercise wrap-up
- 1:10:09Horizontal reduction and floating-point nuances
- 1:22:35Narrowing and widening operations
- 1:31:17Understanding RISC-V intrinsics
- 1:37:18Adler-32 exercise introduction
- 1:40:55Wrap-up and additional resources
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