RISC-V Architectural Certification Tests Early Adoption Workshop
summary
Early-release RISC-V certification tooling generates self-checking assembly tests from a CSV/UDB-driven plan, uses sail as the reference model, produces signature files, and drives DUTs (Spike, CoreFive Wall‑E) while collecting RVI trace coverage and SystemVerilog cover reports. The framework compiles DUT‑specific ELFs, ran 73 M/Div tests with 4 failures (divider bug), the RTL fix re-runs and yields all 73 passing, demonstrating practical end‑to‑end verification and coverage measurement.
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chapters (5)
- 0:00Introduction and overview
- 12:53Certification framework explained
- 33:48Live demo setup and execution
- 47:58Debugging and test results
- 52:34Q&A and next steps
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