Computer Architecture 101 and its Future

on YouTube ↗01h 12m

" summary

Covers why Dennard scaling ends and Moore’s cadence slows, how servers now pack ~64–128 cores (two‑way SMT → ~256 threads) at 3–4.5 GHz with hundreds of in‑flight instructions, and why domain‑specific hardware (TPU generations → ~100× per node; multi‑chip systems up to ~10,000 chips) beats general CPUs for ML. Explains the Roofline performance model, why 8‑bit math is ~30–50× cheaper than 32‑bit, the rise of chiplets, HBM’s ~1,000‑wire stacks and High Bandwidth Flash tradeoffs, plus carbon accounting and the four M’s that can reduce emissions dramatically.

AI-written summary · about

" chapters (11)

1. 0:00Introduction
2. 3:33Speaker: David Patterson
3. 5:17Semiconductor manufacturing
4. 7:01Dennard scaling end
5. 15:40Moore's Law slowdown
6. 22:02Domain-specific AI
7. 28:11Energy in AI hardware
8. 33:34Chiplets and high bandwidth memory in modern computing
9. 39:45Q&A: Chip stacks
10. 49:01AI carbon footprint
11. 1:03:23Q&A: Data center power