IBM's POWER10 Processor
summary
POWER10 is a 7nm server chip with 18 billion transistors and two packaging options (single and dual chip modules) that trade energy per core for core count and I/O. It delivers up to 2 TB/s per chip I/O via PowerAXON/OMI, supports memory disaggregation via memory inception with ~50–100 ns additional latency, claims 3x system performance versus POWER9, and embeds matrix math engines that give ~4x per‑core AI throughput and large precision flexibility.
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chapters (24)
- 0:00Intro
- 1:04IBM POWER Processor Technology Roadmap: Today's Discussion
- 1:17POWER10 Design Focus
- 1:59POWER10 Processor Chip
- 3:08Socket Composability: SCM & DCM
- 4:01System Composability: PowerAXON & Open Memory Interfaces
- 4:40System Enterprise Scale and Bandwidth: SMP & Main Memory
- 6:28Data Plane Bandwidth and Capacity: Open Memory Interfaces
- 7:09System Heterogeneity and Data Plane Capacity: OpenCAPI
- 7:34Pod Composability: Power AXON Memory Clustering
- 8:26Memory Clustering: Distributed Memory Disaggregation and Sharing
- 9:05Memory Clustering: Enterprise-Scale Memory Sharing
- 9:39Memory Clustering: Pod-level Clustering
- 10:31System Composability: PCle Gen 5 Industry I/O Attach
- 10:44POWER10 General Purpose Socket Performance Gains
- 11:47Powerful Core = Enterprise Strength + Al Infused
- 13:18Powerful Core : Enterprise Flexibility
- 15:00Security: End-to-End for the Enterprise Cloud
- 16:04Powerful Core : Enterprise Strength
- 18:21Powerful Core : Energy Efficient
- 19:16Powerful Core : Strength & Efficiency
- 19:44Powerful Core : Al Infused Bandwidth and Compute 2x Bytes from all sources
- 22:11Al Infused Core: Inference Acceleration
- 23:22POWER10 SIMD / Al Socket Performance Gains
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