~/talk

IBM's POWER10 Processor

Talkat OpenPOWER Summit NA 2020 · on Tuesday, 2020-09-15· [ai-assisted-development]
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POWER10 is a 7nm server chip with 18 billion transistors and two packaging options (single and dual chip modules) that trade energy per core for core count and I/O. It delivers up to 2 TB/s per chip I/O via PowerAXON/OMI, supports memory disaggregation via memory inception with ~50–100 ns additional latency, claims 3x system performance versus POWER9, and embeds matrix math engines that give ~4x per‑core AI throughput and large precision flexibility.

AI-written summary · about

  1. 0:00Intro
  2. 1:04IBM POWER Processor Technology Roadmap: Today's Discussion
  3. 1:17POWER10 Design Focus
  4. 1:59POWER10 Processor Chip
  5. 3:08Socket Composability: SCM & DCM
  6. 4:01System Composability: PowerAXON & Open Memory Interfaces
  7. 4:40System Enterprise Scale and Bandwidth: SMP & Main Memory
  8. 6:28Data Plane Bandwidth and Capacity: Open Memory Interfaces
  9. 7:09System Heterogeneity and Data Plane Capacity: OpenCAPI
  10. 7:34Pod Composability: Power AXON Memory Clustering
  11. 8:26Memory Clustering: Distributed Memory Disaggregation and Sharing
  12. 9:05Memory Clustering: Enterprise-Scale Memory Sharing
  13. 9:39Memory Clustering: Pod-level Clustering
  14. 10:31System Composability: PCle Gen 5 Industry I/O Attach
  15. 10:44POWER10 General Purpose Socket Performance Gains
  16. 11:47Powerful Core = Enterprise Strength + Al Infused
  17. 13:18Powerful Core : Enterprise Flexibility
  18. 15:00Security: End-to-End for the Enterprise Cloud
  19. 16:04Powerful Core : Enterprise Strength
  20. 18:21Powerful Core : Energy Efficient
  21. 19:16Powerful Core : Strength & Efficiency
  22. 19:44Powerful Core : Al Infused Bandwidth and Compute 2x Bytes from all sources
  23. 22:11Al Infused Core: Inference Acceleration
  24. 23:22POWER10 SIMD / Al Socket Performance Gains
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