Latch-Up 2025
2025-05-02..2025-05-04
Santa Barbara, United States
Latch-Up ·
[Latch-Up 2024, Latch-Up 2025, Latch-Up 2026]
| title | author | length |
|---|---|---|
| Lightning Talks | 23m | |
Several short projects hit actionable milestones: FP lib fixed‑point library shrinks SystemVerilog multiply‑add from ~30 lines to three, is taped‑out and runs… | ||
| Teaching Open Silicon Design in a Quarter: Using Cloud-based Open Agile EDA Platform | Yuchi Miao | 24m |
A quarter-long course builds a full open-source RTL-to-GDS pipeline using Yosys, SV2V, iEDA/IDA (11 components, ~300k LOC) and IHP130/SkyWater nodes, delivered… | ||
| Stronger Together: Europe Unites for Open-Source EDA | Stefan Wallentowitz | 21m |
Europe commits roughly 40 million euros to open-source EDA, splitting into German seed funding and an EU call that requires national co‑funding; the first… | ||
| PeakRDL: An accessible and extensible SystemRDL CSR automation toolchain | Alex Mykyta | 28m |
A demo of PeakRDL shows a pip-installable SystemRDL 2.0 compiler that elaborates register trees and generates SystemVerilog and VHDL RTL, emits C headers and… | ||
| High-Performance Hardware Design with Hardcaml | Rachit Nigam | 23m |
Hardcaml is an OCaml embedded DSL that implements a seven primitives core API and uses a syntax‑directed compiler to emit RTL and also alternate… | ||
| Fixed Point Numeric Types for Hardware Description | David Hossack | 17m |
Claims a compact numeric model and a working prototype: a Julia library that implements bounded and modular integers and a fixed‑point type, uses an exponent… | ||
| bsg_pearls: Effortlessly Synthesizable Building Blocks That Work Right Out of the Shell | Dan Ruelas-Petrisko | 20m |
A library of mid-level, silicon‑proven modules (clock generator, delay line, SDR/DDR/LPDDR links, LPDDR controller) ships with SystemVerilog, synthesizable… | ||
| Modeling digital signal processing to confirm frequency response and performance | David Hossack | 18m |
A Julia-based text API and GitHub repo models DSP blocks, computes exact transfer functions for composed multi-rate chains, and extracts frequency response… | ||
| The Sunburst Project phase 2 finale and its results | Hugo McNally | 16m |
Phase 2 delivers usable hardware and verified IP: an open Sonata™ development platform (FPGA board plus full toolchain) with about 125 developer boards… | ||
| Opening | Jonathan Balkind | 08m |
About 100 attendees register for a two‑day program Friday–Saturday with an unconference Sunday, talks timed at 15–25 minutes and lightning sessions at the… | ||
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