Open Source SCR1 core

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" summary

SCR1 is an open-source MCU-class RISC-V core that ships on GitHub with configurable RTL, QuickStart guides, tests and simulation scripts and an SDK repository. It implements RV32I/IMC options, offers an optional debug subsystem updated to the RISC-V debug spec, and provides pre-built images for several FPGA platforms. Tooling includes support for major simulators and added Verilator waveform generation. The core is used in both educational exercises and commercial projects worldwide.

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" chapters (6)

1. 0:00Intro
2. 0:13About Intercore
3. 0:36GitHub Page
4. 1:33Configurations
5. 1:54Simulations
6. 2:27SDK

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