~/talk

Open-source model checkers: Ready for the industry?

Talkat ORConf 2019 · 2019-09-27..09-29· [compilers-and-language-design]
links:none on file
slides:none on file

An experimental comparison of several open-source model checkers for Verilog, evaluating their Verilog support and property-checking on both typical and industrial-scale modules using open benchmarks. Also presents Retrascope, an open-source tool that verifies Verilog against SVA properties and provides HDL analysis, model reconstruction and visualization, plus using those models for test generation and property checking.

AI-written summary · about

  1. 0:00Intro
  2. 0:19Formal Verification in HDL
  3. 2:34HDL Model Checkers: History
  4. 5:02Problem statement
  5. 6:36Tool Overview
  6. 7:27Retrascope Toolkit (1)
  7. 9:09Hardware benchmarks
  8. 10:02Selected Verilog benchmarks
  9. 10:24Experiment #1: Verilog support
  10. 11:28Experiment #1: Results
  11. 13:00Experiment #2: Property checking
  12. 15:53Case study
  13. 16:57Conclusion
  14. 18:37Unsupported (but correct!) Verilog
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