Open-source model checkers: Ready for the industry?
summary
An experimental comparison of several open-source model checkers for Verilog, evaluating their Verilog support and property-checking on both typical and industrial-scale modules using open benchmarks. Also presents Retrascope, an open-source tool that verifies Verilog against SVA properties and provides HDL analysis, model reconstruction and visualization, plus using those models for test generation and property checking.
AI-written summary · about
chapters (14)
- 0:00Intro
- 0:19Formal Verification in HDL
- 2:34HDL Model Checkers: History
- 5:02Problem statement
- 6:36Tool Overview
- 7:27Retrascope Toolkit (1)
- 9:09Hardware benchmarks
- 10:02Selected Verilog benchmarks
- 10:24Experiment #1: Verilog support
- 11:28Experiment #1: Results
- 13:00Experiment #2: Property checking
- 15:53Case study
- 16:57Conclusion
- 18:37Unsupported (but correct!) Verilog
related talks
18mRISC-V Spotlight: Improving RISC-V Quality with Verification Standards and Advanc...
21mThe New Verification Ecosystem that Supports RISC-V Verification fo...
17mDemo: RISC-V Models for Verification, Software Development and Architectural Explor...
11mDemo: More Than Point Tools: RISC-V Solutions
18mThe Essence of Verilog: A Tractable and Tested Operational Semantics for Verilo...
19mExploiting Sophisticated Static Analysis for Verilog
51mSynthesis and Verification for All
53mSemantics-based program manipulation in the age of LLMs
