Reusing HW Components with DUH Flow
summary
DUH is an open-source JSON-based data format for describing reusable hardware IP: ports, bus interfaces, memory maps, registers, generator parameters, clocks, resets, etc. The talk covers DUH’s tooling ecosystem — importers from Verilog, IP-XACT and SystemRDL, inference tools to detect standard bus interfaces, a browser viewer and schema validation, and exporters to Verilog, IP-XACT and Chisel/Scala — aimed at improving hardware IP reuse and SoC automation.
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chapters (6)
- 0:00DUH Flow introduction
- 4:14Component composition core
- 9:51System integration design
- 15:46Open source contributions
- 20:00Design systems flexibility
- 22:59Q&A
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