RudolV: from the RISC-V SoftCPU Contest to a Timing-Predictable Core

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" summary

RudolV is a 5-stage in-order RISC-V CPU core designed for timing predictability by avoiding speculative features such as out-of-order execution, dynamic branch prediction, and caches. It explores improving throughput while maintaining predictability using techniques like instruction fusion, in-order dual-issue, and decoupled instruction fetching.

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" chapters (8)

1. 0:00Real-time systems and RISC-V
2. 2:09RudolV project origin
3. 6:27Performance challenges
4. 9:05Security in SoftCPU
5. 13:11Hardware costs in RISC-V
6. 17:44SoftCPU performance improvements
7. 20:02Workshop insights
8. 21:56Summary

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