UltraSoC Presentation
summary
UltraSoC supplies on‑chip monitoring IP that aggregates processor and bus trace across heterogeneous SoCs and claims to cut verification and integration time and cost, supporting RISC‑V for more than two years and deployed by customers including Western Digital. The product exposes a Eclipse‑based IDE with GDB compatibility, works with OpenOCD/monicor tools, captures high‑speed bus and memory transactions and embedded logic analyzer signals via a hardware trace fabric, and presents unified cross‑core trace for faster root‑cause debugging.
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chapters (12)
- 0:00Introduction to UltraSoC
- 1:53UltraSoC in RISC-V ecosystem
- 3:02RISC-V crossing into mainstream
- 5:36Understanding complex SoC development
- 8:05Cost and verification challenges
- 10:13RISC-V standards and maturation
- 11:23Safety and security in RISC-V
- 12:26Open-source vs commercial tools
- 14:14Innovation and ecosystem power
- 16:19Execution over ideas in RISC-V
- 17:22RISC-V crossing the chasm
- 18:48Conclusion and future outlook
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