Computer Architecture, C++, and High Performance
summary
Concrete claims and repeatable measurements: microarchitecture matters more than abstract big‑O, loop unrolling doubles speed on real CPUs, and careful data layout (vector/flat_set vs node set) yields multiple× faster lookups. Tools used are concrete: perf/Intel PCM/IACA and liquid plus assembly/CFG inspection, producing assembly, port utilization and CPI breakdown. Surprising numbers appear: 15 ns DRAM latency and >2000× gap between FLOPs and memory costs, a 130‑cycle budget per packet at 10GbE, and prefetch tuning that halves L3 miss rate and doubles throughput. Experimental, measurable, and actionable.
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chapters (8)
- 0:00Moore's Law and performance trends
- 3:39Single-threaded to multi-core shift
- 11:08Benchmarking container performance
- 21:49Instruction-level parallelism with loop unrolling
- 31:21Optimizing with Intel Architecture Code Analyzer
- 43:10Performance monitoring with Intel PCM
- 51:05Memory locality and cache efficiency
- 1:03:11Summary and key takeaways
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