The Big-endian RISC-V Linux Adventure
summary
Runtime-configurable big-endian RISC‑V is implemented end-to-end: CSRs control endian bits and the project modifies Linux kernel, QEMU, OpenSBI, CVA6 and kvmtool to boot and run a big‑endian kernel under emulation and on Genesis2 hardware. Work exposes real fixes—MMIO and instructions stay little‑endian, lots of code assumes little‑endian, hand‑assembled instructions must be reworked, and CVA6 adds a byte‑swapping block in load/store units while atomic ops use AXI’s BE support. Known problems include OpenOCD crashing when the target is big‑endian and several niche upstream patches.
AI-written summary · about
chapters (6)
- 0:00Introduction to project
- 1:02Why big-endian RISC-V
- 2:31Software stack changes
- 6:46CVA6 modifications
- 11:48Upstreaming challenges
- 12:50Q&A on bit manipulation
related talks
26mThe Big-endian RISC-V Linux Adventure
50mInitializing RISC-V A Guided Tour for ARM Developers
03mIntroduction
25mPreparing RISC-V Linux for RVA23
14mLinux on RISC-V
44mOpenEmbedded/Yocto on RISC-V - New Kid on the Block
01h 00mHow to run Linux on RISC-V (with open hardware and open source FPGA tools)
19mLinux on RISC V Fedora and Firmware Status Update