Verifying a Complex RISC-V Processor Using Test Generation and Hardware Emulat...

on YouTube ↗18m

" summary

Demonstrates a Synopsys workflow that runs XiangShan on FPGA/emulation (Zebu/Haps) with Sting/SRM generating many self-checking ELF files using a reference model and streaming them via a streaming interface into the emulation box so hardware never idles. Results: four-core XiangShan runs show >6,000× speedup over RTL simulation from emulation, and an additional 4× improvement from streaming (70 SRM tests finish in ~4 minutes vs 16 minutes), plus integrated software/hardware trace-driven debug.

AI-written summary · about

" chapters (6)

1. 0:00Introduction and overview
2. 3:12Verification challenges in RISC-V
3. 6:25Hardware-assisted verification solution
4. 8:38Implementation details and results
5. 15:28Summary and future plans
6. 16:31Q&A session

" related talks

• 46mRISC-V Open ISA’s Shock Wave of Processor Innovation Causing Seismic ShiftMike Thompson, Simon Davidmann, Ann Mutschler, Richard Ho, Emerson Hsiao, Dave Kelf, Frank Schirrmeister · RISC-V Summit 2019
• 14mDemo: STING Design Verification: A Robust Approach for Complex RISC-V CPU and SoC ValidationJevin Saju John · RISC-V Summit North America 2023
• 14mSVM: A Synthesizable Approach to Efficient RISC-V CPU VerificationYinan Xu · RISC-V Summit Europe 2026
• 24mRISC V Processor Verification based on Open source FrameworkLee Moore, Richard Ho · RISC-V Summit 2019
• 13mIntroduction to RISC-V Processor VerificationLarry Lapides · embedded world 2022
• 23mOpen Source Verification Platform for RISC V ProcessorsTao Liu, Richard Ho · RISC-V Summit 2019
• 15mThe RISC-V Verification Ecosystem with Open Standards and Commercial ToolsJon Taylor · RISC-V Summit Europe 2023
• 23mThe Continuum of RISC-V Compliance and Verification TestingSimon Davidmann, Allen Baum · RISC-V Summit 2022