W. Han
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- A. Suttononce
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| title | conference | date |
|---|---|---|
| Verifying a Complex RISC-V Processor Using Test Generation and Hardware Emulat... | RISC-V Summit North America 2025 | 2025-10-22 |
Demonstrates a Synopsys workflow that runs XiangShan on FPGA/emulation (Zebu/Haps) with Sting/SRM generating many self-checking ELF files using a reference… | ||
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