The Two Memory Models
summary
Compares the C++ memory model to CPU models and shows concrete examples: making the ready flag an atomic with acquire/release turns the red (racy) arrows green so initialized data happens before use, while relaxed fails. Demonstrates GCC O3/14.1 emitted code differences: x86 needs no fences because of TSO (x86) store ordering, RISC‑V requires compiler-inserted fences or fence instructions. Explains store buffers, out-of-order execution, and when fences actually prevent reorders.
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chapters (9)
- 0:00Introduction
- 1:32Theoretical study
- 8:18Single-threaded reordering
- 19:38CPU and compiler constraints
- 28:44Happens-before in C++
- 32:31Atomic operations and ordering
- 43:06CPU memory models
- 55:26Relaxed models trade-offs
- 1:00:00Summary
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