Low Power AI Edge Hardware
summary
Company ships four chips in two years and a tiny domain‑specific NPU matrix with 28,000 memory cores and dataflow architecture instead of a CPU instruction set. Two products are in production: an MRAM design that runs multiple neural networks concurrently and a low‑power chip claiming 16.8 TOPS at 300 MHz (peak ~24 TOPS/W) while typical parts run <0.4 W. Rack builds include a Sequencer card cluster (16 blades ≈352 TOPS) and a PCIe second generation server delivering ~4,000–4,500 TOPS. Chip already implements MPEG neural‑network parts 13/15/17 and an SDK is underway with Linaro.
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chapters (9)
- 0:00Introduction and company overview
- 2:57Technology and chip design
- 5:45Product lineup and applications
- 9:02Performance comparison
- 10:27Vision and AI capabilities
- 12:16Applications and partnerships
- 13:21Server solutions overview
- 14:53MPEG-7 standard support
- 18:22Future collaboration and SDK
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