Arm-SVE enabled post-K processor
summary
A64FX with Arm‑SVE CPU targets energy‑efficient exascale by pairing A64FX with Arm‑SVE cores (48 compute + 2 OS threads) and on‑package 32 GB HBM2 per chip (≈250 GB/s per stack, ≈1 TB/s total), reaching about 2.7 TF peak per chip and measured ~90% memory bandwidth efficiency; system plan is ≈150,000 nodes (~7.2 million cores) with a Tofu‑style interconnect (6.8 GB/s links, DMA in the NIC) and software support for FP16/INT8; single‑pipe power mode and reported ~100× application speedup over K for selected codes.
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chapters (6)
- 0:00Introduction to Post-K project
- 6:09Architecture overview of Post-K
- 13:20SVE and vector instruction set
- 17:30Interconnect and performance improvements
- 23:02Power efficiency and KPIs
- 26:32Timeline and future plans
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