Sandro Pinto
where else to find them
no profile links on file
what they talk about
where they keep going back
- Black Hat Asia2 editions2020–2023
- RISC-V Summit2 editions2019–2022
all 5 in the filters
on a stage with
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who talks about the same things
- Yueqi Chen6 talks
- Will Deacon6 talks
- Zicheng Wang3 talks
- Kaiwan Billimoria4 talks
- Miklos Balint5 talks
- Marc Zyngier4 talks
| title | conference | date |
|---|---|---|
| Building a Multi‑Guest Virtualized System with Bao on CVA6 in Automotive | RISC-V Summit Europe 2026 Developer Workshops | 2026-06-08 |
Hands‑on build of a multi‑guest system on a CVA6 (MCU, no MMU) using the Bao hypervisor, QEMU/docker flows and FPGA bitstreams; the workshop implements CVA6… | ||
| RISC-V Needs More Secure “Wheels”! A Perspective for/from Automotive Industry | RISC-V Summit North America 2024 | 2024-10-22 |
Argues RISC-V needs richer isolation for zonal automotive ECUs, claiming WorldGuard’s current 32-ID limit (Xilinx 32-bit) won’t scale and realistic designs… | ||
| SoK: Where’s the “up”?! A Comprehensive (bottom-up) Study on the Security of... | WOOT '24 | 2024-08-12 |
Comprehensive audit collects over 7,000 firmware samples and validates 1,797 real-world firmware, scans ~500 related CVEs, and releases tooling on GitHub; key… | ||
| Hand Me Your SECRET, MCU! Microarchitectural Timing Attacks on Microcontrollers are Practical | Black Hat Asia 2023 | 2023-05-09 |
Researchers expose a new bus arbitration timing side channel on ARM Cortex‑M MCUs that leaks secrets by measuring delays when CPU and DMA/peripherals contend… | ||
| Tutorial: Virtualization | RISC-V Summit 2022 | 2022-12-13 |
Covers the RISC‑V hypervisor extension (ratified, adds HS/VS CSRs and VMLOAD/VMSTORE), demos show KVM on QEMU (chemo), Xvisor bare‑metal, and Bao running… | ||
| May the Trust be with You: Empowering TrustZone-M with Multiple Trusted Environments | Black Hat Asia 2020 | 2020-09-29 |
Claim: TrustZone‑M’s dual-world model is too big and brittle, so a new microkernel splits an MCU into isolated multiple trusted worlds. Implementation: a 6 KB… | ||
| How to Secure a RISC V System in 90 minutes From Single Core MCU to Mixed | RISC-V Summit 2019 | 2019-12-09 |
Hands-on pipeline shows an open Rocket-based SoC built from GitHub, an FPGA bitstream flashed to an X300 board with Vivado and OpenOCD, debugged with… | ||
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