Keith Graham
where else to find them
no profile links on file
what they talk about
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where they keep going back
- RISC-V Summit North America2 editions2023–2024
all 4 in the filters
on a stage with
- Jenn Winikusonce
- Ray Simaronce
- Sarah Harrisonce
all 4 in the filters
who talks about the same things
nobody close enough yet
| title | conference | date |
|---|---|---|
| Say Goodbye to Fear, Uncertainty, and Doubt: Innovate with Codasip Studio Fusion | RISC-V Summit North America 2024 | 2024-10-22 |
Codasip Studio Fusion pairs formally verified L110/L730 cores with a workflow for bounded customization that adds custom instructions without breaking formal… | ||
| Software Engineers Are Tomorrow's Processor Engineers | RISC-V Summit North America 2024 | 2024-10-22 |
RISC‑V plus Codasip tooling lets software engineers specify custom instructions using C‑like headers and codal files that generate opcodes and libraries, so… | ||
| AI custom Software/Hardware Interface improving performance 5-10x | RISC-V Summit Europe 2024 | 2024-06-24 |
Customizing a RISC‑V core via Codasip Studio’s Codasip Fusion adds bounded micro‑accelerators (about 3,000 lines of RTL) to speed a sensor + MCU anomaly… | ||
| Why RISC-V? | RISC-V 101 2023 | 2023-11-06 |
RISC-V enables incremental on-chip customization so a small core gains domain-specific resources without breaking base software compatibility, reducing area… | ||
| Why RISC-V Through ISA Customization Demonstration | RISC-V Summit North America 2023 | 2023-11-06 |
Demonstrates RISC‑V ISA customization using Codasip Studio to add new instructions, rebuild the SDK and generate IA/CA models and RTL; a two‑instruction… | ||
| Panel: RISC-V in Education and Training: Successes and Gaps | RISC-V Summit 2022 | 2022-12-13 |
Panel summarizes concrete wins and gaps: several universities convert courses from ARM/MIPS and run hands‑on labs that boot Linux on configurable cores (RV32I… | ||
| nothing matches | ||