Balaji Baktha
where else to find them
no profile links on file
what they talk about
where they keep going back
- RISC-V Summit North America2 editions2023–2024
on a stage with
who talks about the same things
nobody close enough yet
| title | conference | date |
|---|---|---|
| From Momentum to Mainstream | RISC-V Summit North America 2024 | 2024-10-22 |
Claims that Veron V2 is the first high‑performance data center RISC‑V CPU that bridges the x86/ARM performance gap, backed by a shipped chiplet system plus an… | ||
| Keynote: Racing to Adoption: From Momentum to Mainstream with RISC-V | RISC-V Summit North America 2023 | 2023-11-06 |
Ventana announces V2 as a follow-on CPU that pushes IPC about 40% over V1, adds full vector support, a three‑level cache (1.5 MB private per core, up to 120 MB… | ||
| Paving the Road Ahead: RISC-V and Chiplet Technologies in Modern Automotive & More | RISC-V Summit Europe 2023 | 2023-06-05 |
Claims a RISC‑V 16‑core compute cluster with L1/L2/L3 caches and a coherent fabric that matches or beats incumbent single‑socket performance, delivered as a… | ||
| RISC-V FutureWatch | RISC-V Summit 2022 | 2022-12-13 |
Ventana announces a taped-out data-center RISC‑V chiplet processor, Ventana V1 5nm 3.6GHz, claiming single‑socket performance comparable to x86 and high‑end… | ||
| RISC-V Readiness for Datacenter Deployments | RISC-V Summit 2022 | 2022-12-13 |
Ventana claims a RISC‑V data‑center processor that matches incumbent CPU performance while improving efficiency, delivered as a chiplet with hardware PDK and… | ||
| RISC-V Spotlight: Ventana Brings RISC-V to Data Center with Veyron V1 | RISC-V Summit 2022 | 2022-12-13 |
Veyron V1 claims to be the first RISC‑V data‑center class CPU: a 5nm multi‑chiplet SOC with a wide out‑of‑order core, 1MB L2 per core and 64MB cluster L3… | ||
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