Larry Lapides
where else to find them
no profile links on file
what they talk about
all 4 in the filters
where they keep going back
- embedded world3 editions2019–2023
- RISC-V Summit North America2 editions2024–2025
all 4 in the filters
on a stage with
- Rick O'Connoronce
who talks about the same things
nobody close enough yet
| title | conference | date |
|---|---|---|
| Demo: More Than Point Tools: RISC-V Solutions | RISC-V Summit North America 2025 | 2025-10-22 |
Synopsys presents a full RISC‑V stack claim backed by numbers not marketing fluff: ASIP Designer and Platform Architect for architecture exploration, the… | ||
| Demo: More Than Point Tools: RISC-V Solutions | RISC-V Summit North America 2024 | 2024-10-22 |
Synopsys presents a full RISC-V flow: formal model checking and assertion IP covering the ISA, dynamic verification with the Imperas FPM reference model… | ||
| Make vs. Buy on RISC-V | RISC-V 101 2023 | 2023-11-06 |
Decision checklist for RISC‑V cores: choose among ~3 dozen commercial IP vendors (SiFive claims ~350 design wins), serious open‑source projects (lowRISC… | ||
| Introduction to RISC-V Processor Verification | embedded world 2023 | 2023-03-14 |
Processor verification is roughly five times harder than SoC work, so projects use a mix of post‑simulation trace compare and asynchronous continuous compare… | ||
| Demo: RISC-V Models for Verification, Software Development and Architectural Explor... | RISC-V Summit 2022 | 2022-12-13 |
Demonstrates a configurable RISC‑V reference model and simulator that implements the full ratified spec plus stable extensions, supports vendor cores and easy… | ||
| Introduction to RISC-V Processor Verification | embedded world 2022 | 2022-06-21 |
Covers five simulation-based DV flows from simple post-simulation trace compare to asynchronous co-simulation step-and-compare and claims the latter handles… | ||
| Getting Started with RISC-V Custom Instructions | embedded world 2022 | 2022-06-21 |
Imperas uses instruction-accurate simulation and a custom-extension library to add RISC-V instructions, then profiles C code to prove benefit. A ChaCha20… | ||
| Imperas | Embedded World 2019 | 2019-02-26 |
Imperas provides instruction-accurate virtual platforms that model RISC‑V cores and let teams add peripheral and SoC models, run the actual compiled binaries… | ||
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