embedded world 2022
2022-06-21..2022-06-23
Nuremberg, Germany
[embedded world 2016, embedded world 2018, Embedded World 2019, embedded world 2021 DIGITAL, embedded world 2022, embedded world 2023]
| title | author | length |
|---|---|---|
| Remote Development with SCRx-based SDK | Hugo Décharnes | 10m |
Syntacore demonstrates remote debugging of RISC‑V systems using the Syntacore SDK with gdbserver and standard toolchain components (GCC, GDB, QEMU) from a… | ||
| Running Quake on RISC V with Virtual Platforms | Kevin McDermott | 11m |
Imperas builds a RISC‑V virtual platform with a full reference model and peripheral emulation that boots Linux, runs drivers and user code, and exposes… | ||
| NOEL-V, a Configurable 32-Bit and 64-bit RISC-V IP | Christian Sayer | 14m |
Configurable RISC‑V IP that implements RV32I–RV64GC profiles, available under GPL or commercial license, and shipping with GCC/LLVM toolchains, a low‑level… | ||
| Customizing RISC-V Cores to Accelerate Neural Networks | Jon Taylor | 12m |
Demonstration shows the Codasip L31 core extended with a small AI accelerator and custom instructions (notably a pushconf instruction plus a FIFO register… | ||
| SiFive Vector Processor Portfolio | Andrew Frame | 16m |
SiFive offers Linux-capable vector CPUs with concrete specs: P270 256-bit targets smallest-area multi-core in-order designs, while X280 512-bit with SiFive… | ||
| Introduction to RISC-V Processor Verification | Larry Lapides | 13m |
Covers five simulation-based DV flows from simple post-simulation trace compare to asynchronous co-simulation step-and-compare and claims the latter handles… | ||
| The Next Step in Low Energy Edge DSP and AI | Martin Croome | 18m |
GAP9 is a RISC‑V AI/DSP chip combining an MCU, a 9‑core compute cluster, a dedicated smart filtering unit for sample‑by‑sample audio, and an NE16 neural… | ||
| Design for Differentiation: Architecture Licenses in RISC-V | Filip Benna | 13m |
Codasip presents an end-to-end way to change RISC-V ISAs: a high-level processor description language Codal and generator Codasip Studio that produce… | ||
| Developing Containerized RISC-V Applications with Ubuntu | Heinrich Schuchardt | 07m |
Ubuntu adds full RISC-V support with 63,000 packages already rebuilt and preinstalled images for Unmatched/Unleashed, now offering an installer image. Docker… | ||
| Getting Started with RISC-V Custom Instructions | Larry Lapides | 11m |
Imperas uses instruction-accurate simulation and a custom-extension library to add RISC-V instructions, then profiles C code to prove benefit. A ChaCha20… | ||
| I Fought the Law and the Law Lost: Moore’s Law, Dennard Scaling & RISC-V | Rupert Baines | 14m |
Moore’s Law and Dennard scaling have stopped and cost per transistor rises, so architectural innovation becomes the lever. Codasip’s Studio EDA plus an… | ||
| Linux Made Easy on RISC-V with Ubuntu | Gordan Markuš | 09m |
Ubuntu publishes a runnable RISC‑V server image (Jammy 22.04) usable on QEMU and the SiFive Unmatched as a preinstalled image and installer, and the same image… | ||
| SiFive Intelligence X280 | Drew Barbier | 13m |
Update to the SiFive Intelligence X280 adds a VCIX vector coprocessor interface that maps vector registers into the instruction stream so custom accelerators… | ||
| Thermal (IR) Imaging Camera including ISP on Polarfire RISC-V FPGA SoC | S Thomas | 09m |
A complete thermal ISP runs on a PolarFire SoM (CMSV_A1_PF254_AX) with Linux, using an uncooled bolometer Lynred Pico640 640x480 sensor; the pipeline (tone… | ||
| Ubuntu Core: A Secured Embedded Linux Distribution for RISC-V | Ondrej Kubik | 12m |
Ubuntu Core runs on RISC-V with a real QEMU image and board ports, using kernel snap plus a per-board gadget snap and snapd to deliver a 200 MB-ish immutable… | ||
| Securing SiFive Vector Processors with an Open, Scalable Security Architecture | Dany Nativel | 12m |
WorldGuard attaches a world id tag to every CPU transaction and propagates it through caches, interconnect and peripherals, enforcing ACLs… | ||
| OpenHW CORE-V MCU DevKit for Cloud Connected IoT | Rick O'Connor | 13m |
Demonstration shows an open-source RISC‑V CV32E40P core instantiated in a CORE‑V MCU DevKit (emulated on FPGA, 22FDX tapeout pending, silicon expected late… | ||
| RISC-V and Functional Safety | Florian Wohlrab | 21m |
Claims RISC‑V is production ready for automotive with Andes’ N25F core already offered as a functional‑safety variant, company processes certified against ISO… | ||
| Open Acceleration for RISC-V – Portability, Performance and Partners... | Charles Macfarlane | 24m |
SYCL serves as an open standard alternative to CUDA that port applications to RISC‑V with SYCLomatic automated conversion, then auto‑tuning and targeted hand… | ||
| nothing matches | ||