Securing SiFive Vector Processors with an Open, Scalable Security Architecture
summary
WorldGuard attaches a world id tag to every CPU transaction and propagates it through caches, interconnect and peripherals, enforcing ACLs (read‑only/read‑write) at destinations so memory, caches and crypto engines are isolated. Hardware markers and checkers sit on AXI and TileLink with a protected control port; CPU tiles expose hard‑wired machine‑mode world ids and configurable lists for supervisor/user modes. Implementation supports unlimited domains, up to 32 slots per checker and is x280 shipping production‑ready.
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chapters (8)
- 0:00Introduction to World Guard
- 1:29Mechanism and benefits
- 2:38Secure debugging and integration
- 3:32Production readiness
- 4:03Core configuration and logic
- 6:40System-level implementation
- 8:20Markers and checkers explained
- 10:20Roadmap and future outlook
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