Pepijn de Vos
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- Dan Gisselquist5 talks
- Ethan Sifferman2 talks
- Tomasz Hemperek2 talks
- Yann Herklotz4 talks
- Karol Gugala12 talks
- Staf Verhaegen9 talks
| title | conference | date |
|---|---|---|
| Open Source Formal Verification in VHDL | ORConf 2019 | 2019-09-27 |
GHDL now synthesizes VHDL into Yosys via a GHDL→Yosys plugin and supports PSL in VHDL‑2008 so SymbiYosys can run SMT solvers on designs. A hand‑built… | ||
| Synthesize HDL to 7400 logic | ORConf 2019 | 2019-09-27 |
Workflow uses Yosys to synthesize HDL down to 74‑series logic via a Liberty file, exports JSON, and a script generates a KiCad netlist for place‑and‑route and… | ||
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