Luis E. Rueda G.
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| title | conference | date |
|---|---|---|
| ASICone, from Verilog to GDSII with open source tools | ORConf 2019 | 2019-09-27 |
ASICone attempts a full tape-out of a RISC‑V 32‑bit microcontroller on X‑Fab 180nm CMOS using only open‑source tools. The team actually generates standard… | ||
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