ORConf 2025
| title | author | length |
|---|---|---|
| Opening | Matt Venn | 06m |
Opening covers site logistics and community rules: registration and code of conduct, Wi‑Fi access details, AV hiccup from three missing DHL boxes and a patched… | ||
| Open source EDA for Machine Learning | Tom Spyrou | 12m |
Open Road is an open source RTL‑to‑GDS physical design and synthesis flow used for tape‑outs down to 12 nm and being pushed for estimation at ~2 nm, with… | ||
| HAgent an open framework to build hardware agents | Jose Renau | 13m |
HAgent is an open-source framework (https://github.com/masc-ucsc/hagent) that integrates LLMs with chip design tools using a compiler-like pipeline of hermetic… | ||
| Surfer - recent and upcoming development | Oscar Gustafsson | 13m |
Surfer is a Rust waveform viewer built on egui that runs on Linux, Windows, macOS and as WASM and a VS Code plugin from the same codebase. It already reads… | ||
| Guix for FPGAs | Cayetano Santos | 13m |
Claim: Guix replaces ad-hoc FPGA tool and IP installation with a fully declarative, reproducible workflow that lets projects declare dependencies in a guix… | ||
| Open source tools for faster, traceable and reliable development and verification | G. Latosinski | 13m |
Shows how to connect a suite of open source tools to produce code, docs, tests and coverage from one project and a sample design: register specs generate RTL… | ||
| cocotb 2.0: celebrating 12 years of verification fun | cocotb maintainers | 16m |
cocotb 2.0 cleans up long-standing surprises: dozens of small fixes and some deliberate API breaks to make functions behave as named, for example… | ||
| Advancing design verification with Verilator | Krzysztof Bieganski | 13m |
Project progress shows 21 of 33 UVM cookbook examples passing and the tool can now elaborate all of UVM 2017 without workarounds. Recent additions include… | ||
| Constrainedrandom - a Python package that does what it says on the tin | William Keen | 12m |
A Python package that solves constrained-random generation by walking the state space randomly rather than exhaustive solving, giving about a 10x speedup over… | ||
| 10 Years of Chisel | Jack Koenig | 15m |
Fifteen‑year project with ten years of direct involvement; Chisel 7.0 ships new features: probes (XMRs), properties (metadata), layers that can lower to… | ||
| Experience with Chisel in designing a scalable, manufacturable cache directory | Marteen Boersma | 12m |
Implements a synthesizable pipeline cache directory for multi‑CPU coherency using Chisel and generating FIRRTL, verifies with Python UVM over cocotb using both… | ||
| Slang Language Server: Accelerated, Reliable SystemVerilog Development | Andrew Nolte | 12m |
Built on Slang and released as slang-server (github.com/hudson-trading/slang-server), the tool claims IDE-grade SystemVerilog features with real numbers… | ||
| Dyno-SV: A new IR-driven open-source RTL synthesis tool | Mathis Salmen | 14m |
Dyno-SV implements a new IR called Dyno-IR rather than reusing Yosys or MLIR, representing designs from behavioral to gate level and delaying control-flow… | ||
| Yosys + egglog: supercharge your passes with equality saturation | Gus Henry Smith | 14m |
Prototype Yosys plugin converts RTL into an egraph via egraph ingestion and expansion, runs many rewrites simultaneously (examples shown: commutativity and a… | ||
| najaeada - Getting closer to an industrial grade ECO solution with an open source stack | Noam Cohen | 11m |
An open C++ netlist framework naja (C++ framework) plus a Python wrapper najaeda (PyPI) provide Verilog and Liberty parsing, cross‑boundary equal‑potential… | ||
| RISC-V: Hardcore/Softcore Co-Simulation Environment with Cycle-Accurate Rollback | Jérémy Alcim | 12m |
Realtime co-simulation compares a Verilog RISC‑V core with a C softcore via a C++ checker that flags mismatches on resource‑access notifications, enabling… | ||
| Extending RISC-V with SCAIE-V | Tammo Mürmann | 14m |
SCAIE-V (demo named Sky 5) generates RTL to plug custom instructions into multiple RISC‑V cores (PicoRV32, VexRiscv, CVA5, CVA6), supports register/PC/memory… | ||
| Transactron - hardware transactions for Amaranth HDL | Aria Węgrzyn | 15m |
Open-source Transactron for Amaranth HDL provides single-cycle methods and Python context-manager transactions that automatically generate a transaction… | ||
| GDSFactory: Open-Source EDA for Accelerating Photonics, Quantum, MEMS, RF Chip Design | J. Matres | 11m |
GDSFactory is an open‑source Python EDA that claims over 2 million downloads and a 100‑developer community, targeting photonics, quantum, MEMS and RF… | ||
| Wildcat: Educational RISC-V Microprocessors | Martin Schoeberl | 14m |
An open-source RISC-V core implemented in Scala/Chisel shows concrete measurements: three-stage pipeline runs faster and uses fewer FPGA resources than four-… | ||
| Panamax FPGA - An Open Source FPGA on SKY130 | Leo Moser | 14m |
A full FPGA built in the Panamax padframe targeting the sky130 PDK: fabric with 64 I/Os, 1,280 LCs (LUT4+FF), 8 MACs, 16 small register files and 8 BRAM blocks… | ||
| A Sneak Preview into the FABulous 2.0 eFPGA Framework | Jonas Künstler | 15m |
FABulous 2.0 shows concrete upgrades: direct one-click Libra lane → GDS for optimized tiled fabric integration, automated timing-model extraction from ASIC… | ||
| A portable area efficient SRAM compiler: a ... job somebody has to do | Staf Verhaegen | 14m |
A portable SRAM compiler targets IHP SG13G2 with planned ports to Sky130 and GF180MCU, produces both single‑port 6T cells (optionally 8T dual‑port) and full… | ||
| DRAM simulation with the simulator DRAMSys | Matthias Jung | 15m |
DRAMSys is an open-source SystemC TLM-2.0 framework with commercial models for DDR5/LPDDR5/HBM3 and academic free licenses, claiming 400x speedup versus RTL… | ||
| LibreLane: Looking to the future | Mohamed "Donn" Gaber, Leo Moser | 15m |
LibreLane positions itself as a modular, Python-based successor to OpenLane that preserves simple config while adding immutable state semantics so designs can… | ||
| Resizing Your Expectations: Mastering Timing Closure with OpenROAD's Evolving Optimizer | M. Guthaus | 18m |
OpenROAD’s Resizer operates as a physical-synthesis engine that already performs swap VTH, buffering, cloning and load splitting and reports iterative passes… | ||
| Mission-Specific Chips for Space: Open Tools, Real Systems, Radical Performance | Thomas Parry | 10m |
Claims a mission-specific GaN gate‑driver chip built with KLayout and Xschem, manufactured at XFAB, tested with proton irradiation and then through vibration… | ||
| Just how far can you go with FOSS? | Peter Birch | 13m |
Argument: open source silicon and tools take a startup most of the way but not all the way — they enable fast, maintainable flows, team bonding, and community… | ||
| SystemVerilog Assertion Verification with CIRCT | Tobias Wölfel | 16m |
Claims that CIRCT can represent and process concurrent SystemVerilog Assertions by importing slang ASTs and lowering SVA to a CIRCT LTL dialect, with prototype… | ||
| Third Time's the Charm | John Goodenough | 17m |
Three years of experiments at Sheffield embed chip design across undergrad and masters programs using open source assets, claiming enough maturity to teach… | ||
| Shaping Tomorrow’s Chip Designers: Open-Source Initiatives at IHP | C. Wittke, J. Wallenborn | 18m |
IHP releases two five‑day certificate courses (digital and analog/mixed‑signal) as open‑licensed Git repos, run trial cohorts with daily feedback and module… | ||
| EuroCDP: the open branch | Macarena Martinez-Rodriguez | 15m |
EuroCDP’s open branch assembles an OSS toolbox for Level 0 ideation and an OSS sandbox plus accelerator support for Level 1–2 users, and promises an Open IP… | ||
| Realising low cost and simple IC design - ChipFoundry and ChipFlow collaboration | Rob Taylor | 14m |
ChipFlow and ChipFoundry deliver a cloud place‑and‑route platform plus a new graphical SoC builder that runs fully in the browser, can generate software and… | ||
| Open source chip design: for fun and for profit | Andreas Olofsson | 18m |
Company runs an open toolchain and claims production use of multiple projects including SiliconCompiler 2,000 commits 830 files, a cloud co‑simulation platform… | ||
| Tiliqua - Accessible, Reconfigurable Audio DSP Platform | Sebastian Holzapfel | 15m |
Tiliqua is an open hardware module plus Amaranth HDL DSP library running on an ECP5 SOM that loads up to eight bitstreams and produces an eight‑voice… | ||
| nothing matches | ||