Mark Throndson
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| title | conference | date |
|---|---|---|
| Networking-Native RISC-V Processor for Datacenter | RISC-V Summit North America 2025 | 2025-10-22 |
A RISC‑V I8500 core is built for line‑rate packet work: RVB23 with SV39/SV48, big‑endian execution, an in‑order three‑issue pipeline and 4‑way SMT that lets… | ||
| The SiFive Vector Processor | RISC-V Summit 2019 | 2019-12-09 |
SiFive describes a vector roadmap centered on a configured VI2 series core with a 32 register file and 512 bit physical vector registers that software can… | ||
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