Nationally Critical Infrastructure needs Secure Hardware
summary
DARPA’s SIF program funds open RISC‑V designs that implement concrete mitigations and formal proofs rather than vague promises: teams build 18 CPUs on Xilinx VCU118 FPGAs, each instrumented with metadata tagging, enclaves, or pervasive crypto, and the program targets seven vulnerability classes with the first results claiming memory errors and timing side‑channels eliminated. All RTL, firmware and proofs are published for continuous red‑teaming (Def Con demo), and a separate Shield chip that detects microscopy/laser tamper is prototyped.
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chapters (20)
- 0:00Start
- 5:40Galois' Trusted Services Engine
- 10:14Operating System Options
- 11:33System Assurance
- 13:40Assurance Cases Built on Sand
- 15:01The Bridge Between Our Worlds is Broken
- 16:07A Solution Proposed This Decade
- 22:13SSITH in a Nutshell
- 27:18Security-Related R&D
- 32:06DARPA SHIELD
- 34:46What is RISC-V?
- 38:32The State of Voting System Security
- 43:38Bespoke Systems
- 44:55Lever Machines
- 47:54State-of-the-Art Assessment
- 48:34Estonia Sample Code
- 48:51DEF CON Voting Village
- 50:03DARPA Secure Hardware meets Democracy
- 52:13CAD SBB Mechanical Design
- 55:09For More Information
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