~/talk

Mitigating CPU Frontend for Complex Data Plane Applications

on YouTube 17m
Talkat NSDI '26 · 2026-05-04..05-06· [networking]

speakers

name:Yihan Dang
links:none on file
name:Hao Li
links:none on file
name:Ze Xia
links:none on file
name:Jiajun Luan
links:none on file
name:Peng Zhang
links:none on file

resources

video:https://youtu.be/0DQdjUw-Tdg
slides:none on file

summary

Finds CDPAs stall on the CPU front end (45.1% of cycles on average) due to instruction working sets far larger than L1 I‑cache, and builds NanoPL: an offline analyzer that inserts scheduling sites, an LLVM‑IR alias analysis that computes commitment windows, and a runtime scheduler that saves context and pipelines packets across I-cache-friendly stages. Evaluation on real CDPAs shows 17.2%–30.2% throughput gain and up to 86.4% reduction in I‑cache misses, demonstrating the approach reduces frontend stalls without changing program semantics.

AI-written summary · about

chapters (14)

  1. 0:00Introduction
  2. 0:19Motivation behind complex data plane applications
  3. 2:06CPU frontend bottlenecks
  4. 3:53I-cache misses in packet processing
  5. 4:59Limitations of I-cache optimizations
  6. 6:30NanoPipeLine’s core insight
  7. 7:11NanoPipeLine’s processing stages
  8. 8:36Semantic consistency in scheduling
  9. 10:20Cross-packet variable states
  10. 12:06Scheduling site placement efficiency
  11. 13:09Profile-guided I-cache partitioning
  12. 14:17NanoPipeLine’s performance gains
  13. 15:20Performance counters comparison
  14. 16:04Summary

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