Analyzing Packet Data Flow in Chiplet Based SoCs
summary
Chiplet SoCs add a die-to-die link that forces DMA and snoop traffic off-chip, turning DPDK flows (core→NIC, NIC→core, NIC write-back) into extra round trips and memory accesses; descriptors and packet data often land in main memory instead of a shared L3, increasing latency and invalidation stalls. Practical mitigations shown are cache-line demote and DDIO-like stashing, and a proposed Arm feature of stashing to CPU caches to avoid memory trips and reduce snoop-induced delays.
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chapters (8)
- 0:00Introduction to chiplet data flows
- 2:10Monolithic vs chiplet CPUs
- 5:01Basic DPDK data flows
- 10:08Core to NIC and NIC to core
- 13:25NIC write-back complications
- 15:35Packet processing cycle
- 18:29Freeing and refilling buffers
- 20:36Chiplet latency challenges
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