Running DPDK on Non-Cache Coherent Platforms: Challenges and Solutions
summary
Ports DPDK to NXP i.MX non-cache-coherent (NCC) platforms and shows DMA visibility breaks where 16-byte buffer descriptors (BDs) and packet buffers diverge between core caches and hardware. Implementation uses a non-cacheable BD + cacheable buffers hybrid, adds architecture-level rt_cache invalidate/flush APIs, and supplies a kernel kpage module plus two allocation routes: hugepage reservation (mempool-style) or a virtual-socket hugepage allocation in the DPDK library. Measured tradeoff: non-cacheable data buffers drop throughput ~70%, hybrid PMD restores performance and complexity; patches and kernel module are available.
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chapters (10)
- 0:00Introduction and presenters
- 0:44Low-end devices and coherency issues
- 3:12Challenges in Ethernet PMD on non-cache coherent platforms
- 5:22Software workarounds for cache coherency
- 7:50Hybrid solution for PMD implementation
- 12:13Proposed DPDK changes for non-cache coherent support
- 17:18Virtual socket memory allocation approach
- 20:51Performance comparison and recommendations
- 21:55Summary and future steps
- 22:37Q&A session
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