Reexamining Direct Cache Access to Optimize I/O Intensive Applications for Multi
summary
Microbenchmarks on two servers with 100 Gbps NICs show DDIO (Intel DDIO) causes about a 30% increase in 99th‑percentile latency when aggregate receive rate reaches 200 Gbps. Using CAT to probe LLC ways, experiments identify DDIO allocation to two LLC ways and show changing the iio_llc_base register (more bits set) raises DDIO write‑hit rates and cuts tail latency by up to ~30%. Practical fixes—disable DDIO for a NIC or place the NIC on a remote socket—restore 100 Gbps latency while forwarding 200 Gbps.
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chapters (17)
- 0:00Intro
- 0:59Direct Cache Access (DCA)
- 1:32Intel Data Direct I/O (DDIO)
- 2:36Pressure from these trends
- 4:30What happens at 200 Gbps?
- 5:18How does DDIO work?
- 7:05LLC ways used by DDIO
- 9:13How does DDIO perform?
- 9:54Reducing #Descriptors is Not Sufficient! (1/2)
- 11:36IIO LLC WAYS Register
- 12:24Impact of Tuning DDIO
- 13:26Is Tuning DDIO Enough?
- 14:45What about Current Systems?
- 15:27Using Our Knowledge for 200 Gbps
- 17:43Our Key Findings (1/2)
- 19:01Impact of Processing Time
- 20:03Conclusion
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