The nanoPU: A Nanosecond Network Stack for Datacenters
Talkat 15th USENIX Symposium on Operating Systems Design and Implementation (OSDI '21) · 2021-07-14..07-16·
summary
Prototype integrates NIC and CPU on FPGA, adds a register-file fast path that places incoming messages into CPU registers, and a hardware thread scheduler that fires sub-nanosecond context-switch interrupts. Cycle-accurate FireSim results show 69 ns wire-to-wire latency and ~118 million requests/sec per core, 4–6× lower tail latency and ~20% higher sustained load vs traditional scheduling. Implementation modifies Rocket RISC‑V cores, implements NDP, and runs MICA, Raft, Set Algebra.
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chapters (7)
- 0:00Introduction
- 0:26Trends
- 4:24The nanoPU
- 9:34Prototype
- 11:59Applications
- 13:16Onesided RDMA
- 14:12Conclusion
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