Optimizing Storage Performance with Calibrated Interrupts
Talkat 15th USENIX Symposium on Operating Systems Design and Implementation (OSDI '21) · 2021-07-14..07-16
summary
Describes adding a two-bit hint to the NVMe device interface so software (kernel and applications) can mark submitted I/O requests as latency-sensitive; the NVMe device then “calibrates” its interrupt coalescing to fire immediately for those completions while still coalescing other traffic. Evaluates the approach on NVMe storage showing up to 35% higher throughput, 30% lower CPU use, and up to 37% lower latency under coalescing.
AI-written summary · about