Building A CSFQ-Inspired Transport for Switched CXL Memory Pooling
summary
Characterizes an XConn Apollo/Titan switched CXL testbed and shows unmanaged streams cause severe interference — victim bandwidth falls 83% at the host and fabric head‑of‑line stalls slow a flow up to 6.9×. Builds MemChannel, a CSFQ-inspired sender-driven transport implemented end-to-end (no switch changes) that uses time‑based rate control, host admission, cross‑host bookkeeping, new congestion signals and delay‑based capacity adjustments. Evaluations report 4.5x throughput for contended apps and 52% latency reduction while supporting unmodified applications.
AI-written summary · about
chapters (6)
- 0:00CSFQ-inspired CXL pooling intro
- 3:34Switch CXL pooling performance
- 6:01MEM channel design
- 11:27CSFQ for CXL streams
- 14:45MEM channel real workloads
- 15:50Conclusion and future
related talks
12mTwenty Years After: Hierarchical Core-Stateless Fair Queueing
19mSwCC: Software-Programmable and Per-Packet Congestion Control in RDMA Engine
17mCeph Messenger Situation and Optimization
17mBridging the Gap between QoE and QoS in Congestion Control: A Large-scale Mobile...
16mCredence: Augmenting Datacenter Switch Buffer Sharing with ML Predictions
22mLIVE Q&A #3
19mTackling DC Congestion and Bursts
17mPyrrha: Congestion-Root-Based Flow Control to Eliminate Head-of-Line Blocking in...
